Integrated circuits, and particularly memories utilize capacitors in a variety of ways. DRAMs, in particular, employ capacitors to store charge representing a data bit. As the minimum feature size and cell architecture are scaled down, robust design points for DRAM cells utilizing planar metal oxide semiconductor field effect transistors (MOSFETs) and DT capacitors are increasingly difficult to achieve. The vertical MOSFET provides a means for better scaling. However, the back-to-back vertical MOSFET devices in the cell makes it challenging since the p-well doping required to avoid interaction between the back-to-back cells must be increased. In some instances, such increased doping results in a high electric field at the p-n junction between the buried strap outdiffusion and the p-well. This, in turn, can lead to increased junction leakage from the storage node and a degradation in the tail of the distribution of the retention time for cells in the DRAM array. An improved method and structure is needed to permit the vertical transistor DRAM cell to be further scaled while holding junction leakage to within a tolerable limit.